Engineers need to analyze defects and other failures during semiconductor fabrication to troubleshoot, adjust, and improve the fabrication processes. For example, defect analysis is useful in all aspects of semiconductor production including design verification diagnostics, production diagnostics, as well as other aspects of microcircuit research and development. As device geometries continue to shrink and new materials are introduced, the structural complexity of today's semiconductors grows exponentially. Many of the structures created are often interconnected with previous layers. Thus, the defects and structural causes of device failure are often hidden well below the surface.
Accordingly, defect analysis often requires cross-sectioning and viewing defects on a three-dimensional basis. With the growing use of copper conductor devices on semiconductor wafers, better systems capable of performing three dimensional defect analyses are more important than ever. Furthermore, as semiconductor device densities and wafer areas increase, the volume of product diagnostic data required to diagnose yield-limiting defects grows exponentially.
Electrical test data correlation to in-line process defects is called electronic test process limited yield (e-TPLY). The current e-TPLY practice involves removing a wafer from the manufacturing line. This wafer becomes a scrap wafer. The desired die within the wafer is then cut, delayered, and subject to top-down and cross-section inspections. This process is highly manual, and very slow. Typical turnaround time can be as high as five days. Furthermore, the entire wafer has to be scrapped. Since this wafer may contain many good die, scrapping the entire wafer may result in a waste of good chips.
Therefore, what is needed is an improved failure analysis system and method that addresses the aforementioned disadvantages of the current practice.